Non-volatile memory devices, such as electrically erasable and programmable read only memories (EEPROMs), comprise core arrays of memory cells including a variable threshold transistor. Each memory cell can include a number of transistors; at least one of which will be a variable threshold (i.e., programmable) transistor.
With reference to FIG. 1, a portion 100 of a prior art memory array includes a plurality of memory cells 101; each of the plurality of memory cells 101 includes a pair of transistors, a select transistor 101A and a variable threshold transistor (i.e., a floating gate transistor) 101B. According to one version of the prior art, the select transistor 101A is an n-channel enhancement transistor, and the floating gate transistor 101B is an n-channel native transistor. Other kinds of the plurality of memory cells 101 each including a greater number of transistors are known in the prior art as well. Additionally, various arrangements of the plurality of memory cells 101 are known, such as NAND EEPROM and NOR EEPROM arrays.
The plurality of memory cells 101 is each interconnected by a plurality of wordlines lines 103, a plurality of sense lines 105, and a plurality of bitlines 107. In particular, drains of the each of the select transistors 101A are connected to one of the plurality of bitlines 107. A gate of each of the select transistors 101A and the floating gate transistors 101B is each connected to one of the plurality of wordlines 103 and sense lines 107 respectively.
In FIG. 2, a non-volatile memory arrangement 200 of the prior art includes a read select transistor 201, a read select line 201A, a sense amplifier 203, a data bus 203A, and a wordline decoder 205. The non-volatile memory arrangement further includes one each of the select transistors 101A and the floating gate transistors 101B from FIG. 1. As was the case in FIG. 1, according to an n-channel implementation of the select 101A and the floating gate 101B transistors, the drain of the select transistor 101A will be connected to one of the plurality of bitlines 107, and respective gates of the select 101A and the floating gate 101B transistors are connected respectively to one of the plurality of wordlines 103 and sense lines 105. The wordline 103 is driven by a word line decoder 205.
The read select transistor 201 is connected to the read select line 201A. When a read operation is active, the read select transistor 201 is turned on, thereby electrically connecting the bitline 107 to the data bus 203A. The data bus 203A, in turn, is connected to the sense amplifier 203. When the non-volatile memory arrangement 200 is subject to a read operation, a conductive state of the memory cell 101 is queried by connecting the bitline 107 to the sense amplifier 203 and applying appropriate bias voltages to the selected bitline 107, sense line 105, and wordline 103. If the select transistor 101A is turned on and the bias voltage applied to the sense line 105 exceeds a threshold of the floating gate transistor 101B, current will flow from the bitline 107 to ground through the memory cell 101 and the sense amplifier 203 will detect a “low” state. Conversely, if the bias voltage applied to the sense line 105 does not exceed the threshold of the floating gate transistor 101B, then no current will flow through the memory cell 101, and the sense amplifier 203 will detect a “high” state. While the sensing approach just described provides an operable memory arrangement, power consumption levels which characterize this approach are disadvantageous.
Power requirements of a contemporary memory sense amplifier are indicated in the dynamic power requirement, Pdyn, as a function of operating frequency, fop, graph 300 of FIG. 3. A constant sense amplifier consumed power trace 301 is indicative of a minimum power requirement, per wordline, any time the sense amplifier 203 (FIG. 2) is in an operational mode. A minimum sense amplifier power, Pmin, is determined byPmin=Vdd·ISA where Vdd is the system voltage and ISA is the sense amplifier current. A linear expression of total memory array power without sense amplifiers, Parray, 303 is governed byParray=Ccore·Vdd2·fop where Ccore is determined from a total gate-source capacitance, Cgs, value of each of the memory transistors within the plurality of memory cells 101 (FIG. 1). A total dynamic power requirement 305 is then determined byPdyn=(Ccore·Vdd2·fop)+(Vdd·ISA)which is merely a summation of the constant amplifier consumed power 301 and the linear expression of total memory array power without sense amplifiers 303.
The dynamic power, Pdyn, is a function of one variable—operating frequency, fop. Other functional dependencies, Ccore, Vdd, and ISA, are all fixed for a given memory array configuration. Therefore, it is desirable to minimize the total dynamic power requirement, especially in situations where either the operating frequency is variable during memory array operation or a given memory array is adaptable to a range of operating frequencies within a given circuit.